A ferroelectric memory (i.e., a ferroelectric random access memory (FeRAM)) is a semiconductor memory device using a hysteresis property of a ferroelectric capacitor. The FeRAM has memory cells, and each memory cell can store data in a nonvolatile manner based on two different polarization strengths of a ferroelectric material. In a readout operation, data is read from the memory cell to bitlines, a signal representing the read data is amplified by a latch type sense amplifier circuit, and the amplified signal is output to a peripheral circuit. Generally, the bitlines of a FeRAM has a so-called folded bitline structure in which two adjacently opposed bitlines are pared (see JP-2009-099235-A and JP-2010-061734-A). In the FeRAM having the folded bitlines, while data is read from a memory cell as a reading voltage to one of the bitlines, the other of the bitlines is set to a reference voltage. And, the sense amplifier circuit amplifies the difference between the reading voltage and the reference voltage. Then, the sense amplifier circuit outputs a signal corresponding to the amplified level difference.
In a ferroelectric memory, a reading voltage is determined by the capacity of the bitline and the capacity of the memory cell. However, sometimes, the voltage of one bitline is varied due to an influence of the voltage of other bitline through coupling therebetween. In the readout operation, the voltage of a bitline ranges from, for example, about 0.3 volts (V) to about 1V. On the other hand, a signal amount (level difference between the “1” readout signal and the “0” readout signal) of the memory cell ranges from about 0.3 V to about 0.5 V. Thus, the influence of an adjacent bitline causes large variation of the voltage of the bitline.